Combined timing-outpulsing-scanning circuit

ABSTRACT

This invention relates to the architecture of the timer-scanner, one of several common circuits of an automatic test system of an electronic exchange. It performs the various timing functions required in the system and will time intervals from 10 ms to 2 seconds as required. The pre-setting of the timer is performed in response to external signals from the routiner logic.

United States Patent 9] Crosley Nov. 26, 1974 [54] COMBINED 3.265,8678/1966 Venn et a1 235/92 T TIMING OUTPULSINGSCANNING 3,564,217 2/1971Bounsall 235/92 PE CIRCUIT 3,636,549 H1972 Berman et a1... 235/92 T3,789,195 1/1974 Meier et al 235/92 T [75] Inventor: Thomas W. Crosley,Northlake, Ill.

l l FROM CPU FROM OUTPUT REG.

[ 1 Assigneel GTE Autqmafic Electric Primary Examiner1(athleen H. ClaffyLaboratories lncollml'ated, Assistant Examiner-Douglas W. OlmsNorthlake, Ill.

[22] Filed: June 15, 1973 B T 211 App]. No.: 370,560 [57] A STRAC Thisinvention relates to the architecture of the timer- [52 us. C1 179/1752R, 235/92 T Scanner, one of Several common circuits of an auto- 51Int.C1. H04m 3/24 matic test System Of an electronic exchange P 5g Fieldf Search U 23 5 92 T, 2 179/175, forms the various timing functionsrequired in the sys- 179/1752 R tem and will time intervals from 10 msto 2 seconds as required. The pre-setting of the timer is performed in 5References Cited response to external signals from the routiner logic.

. UNITED STATES PATENT S 2 Claims, 11 Drawing Figures 2,970,226 1/1961Skelton et a1 235/132 A TO III I ST I'R EQ EEEYC TO MF/TCMF SENDER HTMR.FF[x] MF,TCMF ENAB. TIMEOUT, TIMEOUT ADVANCE MPLX. DGT BIT [x] FROM cPutOUTPUT REG. PS HTMRLX? DlglT 1, TIMER TIMER m MULTIPLEX LKL PREsETsFLIP-FLOlI ENABLE 9 l9 II I XX MS SCAN\ I HTMR CTRL scAN I ENABLV FROMHTMR I LiJlS'IE' DEC MF/TSCEMTF I SCANNER R T|MER/ I PU SET xx YY/ZZLATCH/.35 CTRL} SCANNER R SCAN T0 6 g'gg CONTROL COUNTER, 4 n;

15 cTRI/ STOP scAN DEC x SCAN slfm CLKSx l/SET LAST DlGlT cTRu Efifi-CLOCK QSE DISTRIBUTOR l6 CLKQ) LOGIC HI SCANNER TIMEOUT MF DGT iMF DGTEXT. CTRL. B|T[X] BIT[X] J X TO CPU INPUT REG. MF REC PATEHTL M619143.851.120

sum 02 0F 10 CLOCKS CLK4 Q) CLK. A v

CLK. B Q

CLK.-C

@ CLK c TRAIL Q) CLK. D 629 CLK. D LEAD I CLK. 0 LEAD @CLK. D TRAIL@CLD. 13 TRAIL NOTE; 256 US CLK. (NOT SHOWN ABOVE) FALLS EVERY EIGHTCYCLES AT THE END OF CLK. C

PSI PS2 P ATENTEL NW 2 6 I974 SHEET 0? BF 1O SCANNER LATCHES ANDNPRESETS 7| (SET MF lOO/ L 7|4 L 3- TO FIG. 3

' 35 Ms REQ.

SEYT- EMF 5/35 FROM MP 551} EXT. INPUTS' TO FIG. 9

I TC 4 5 /45 ITCMF 45 Ms SCAN 'rzo I 1 72! TO FIG. 3

W722 J SET 76 doc MS SCAN MFS I00 I00 W 7.7 723 To F|Gs.6,|0

0- ;MF SCAN SET] c ,scAN ENABLE 'J I 712 TO FIG. 5 l SCAN ENABLE /l INCSCA-N $53] I l g TO FIGS. 5, FROM sToP SCAN l I FIG. 8 I

' SCAN GATEI -TSCAN GATEIh. JSCAN GATEI+11 FROM FIG. 6

CIRCUIT CROSS-REFERENCES TO RELATED APPLICATIONS The preferredembodiment of the invention is incorporated in a COMMUNICATION SWITCHINGSYS- TEM WITH MARKER, REGISTER AND OTHER SUBSYSTEMS COORDINATED BY ASTORED PROGRAM CENTRAL PROCESSOR, US. patent application Ser. No.130,133 now abandoned filed Apr. 1, 1971 by K. E. Prescher, R. E.Schauer and F. B. Sikorski, and a continuation-in-part thereof Ser. No.342,323, filed Mar. 19, 1973, hereinafter referred to as the SYSTEMapplication. The system may also be referred to as No. l EAX or simplyEAX.

The memory access, and the priority and interrupt circuits for theregister-sender subsystem are covered by US. patent application Ser. No.139,480 now Pat.

No. 3,729,715 filed May 3, 1971 by C. K. Buedel for a MEMORY ACCESSAPPARATUS PROVIDING CYCLIC SEQUENTIAL ACCESS BY A REGISTER SUBSYSTEM ANDRANDOM ACCESS BY A MAIN PROCESSOR IN A COMMUNICATION SWITCH- ING SYSTEM,hereinafter referred to asthe REGIS- TER-SENDER MEMORY'CONTROL patentapplication. The register-sender subsystem is described in US. patentapplication Ser.-No. 201,851 now Pat. No. 3,737,873 filed Nov. 24, 1971by S. E. Puccini for DATA PROCESSOR WITH CYCLIC SEQUENTIAL ACCESS TOMULTIPLEXED LOGIC AND MEM- ORY, hereinafter referred to as the REGISTER-SENDER patent application. Maintenance hardware features of theregister-sender are described in four US. patent applications having thesame disclosure filed July 12, 1971, Ser. No. 270,909, now Pat. No.3,784,801, by J. P. Caputo and F. A. Weber for a DATA HANDLING SYSTEMERROR AND FAULT Y DETECTING AND DISCRIMINATING MAINTE- NANCEARRANGEMENT, Ser. No. 270,910, now Pat. No. 3,783,255, by C. K. Buedeland J. P. Caputo for a DATA HANDLING SYSTEM MAINTENANCE ARRANGEMENT FORPROCESSING SYSTEM TROUBLE CONDITIONS, Ser. No. 270,912, now Pat. No.3,805,038, by C. K. Buedel and J. P. Caputo for a DATA HANDLING SYSTEMMAINTENANCE AR- RANGEMENT FOR PROCESSING SYSTEM FAULT CONDITIONS, andSer. No. 270,916, now Pat. No. 3,783,256, by J. P. Caputo and G. OToolefor a DATA HANDLING SYSTEM MAINTENANCE ARRANGE- MENT FOR CHECKINGSIGNALS, these four applications being referred to hereinafter as theREGIS- TER-SENDER MAINTENANCE patent applications.

The marker for the system is disclosed in the US. Pat. No. 3,681,537,issued Aug. 1, 1972 by J. W. Eddy, H. G. Fitch, W. F. Mui and A. M.Valente for a MARKER FOR COMMUNICATION SWITCHING SYSTEM, and Pat. No.3,678,208, issued July 18, 1972 by J. W. Eddy for a MARKER PATH FINDINGAR- RANGEMENT INCLUDING IMMEDIATE RING; and also in US. patentapplications Ser. No. 281,586, now Pat. No. 3,806,659, filed Aug. 17,1972 by J. W. Eddy for an INTERLOCK ARRANGEMENT FOR A COMMUNICATIONSWITCHING SYSTEM, Ser. No. 311,606 filed Dec. 4, 1972 by J. W. Eddy andS. E. Puccini for a COMMUNICATION SYSTEM CON- TROL TRANSFER ARRANGEMENT,Ser. No. 303,157, now Pat. No. 3,809,822, filed Nov. 2, 1972 by J. W.Eddy and S. E. Puccini for a COMMUNICA- TION SWITCHING SYSTEM INTERLOCKAR- RANGEMENT, hereinafter MARKER patents and applications.

The communication register and the marker transceivers are described inUS. patent application Ser.

No. 320,412, now Pat. No. 3,814,859, filed Jan. 2,

1973 by J. J. Vrba and C. K. Buedel for a COMMUNI- CATION SWITCHINGSYSTEM TRANSCEIVER ARRANGEMENT FOR SERIAL TRANSMISSION, hereinafterreferred to as the COMMUNICATIONS REGISTER patent application.

The executive or operating system of the stored program processor isdisclosed in US. patent application Ser. No. 347,281 filed Apr. 2, 1973by C. A. Kalat, E. F. Wodka, A. W. Clay, and P. R. Harrington for STOREDPROGRAM CONTROL IN A COMMUNI- CATION SWITCHING SYSTEM, hereinafterreferred to as the EXECUTIVE patent application.

The computer line processor is disclosed in US. patent application Ser.No. 347,966 filed Apr. 3, 1973 by L. V. Jones and P. A. Zelinski for aSENSE LINE PRO- CESSOR WITH PRIORITY INTERRUPT AR- RANGEMENT FOR DATAPROCESSING SYS- TEMS.

A test system for use within this system is disclosed I BACKGROUND OFTHE INVENTION 1. Field of the Invention This invention relates to acommunication switching system and particularly to a timer and controlarrangement capable of timing a multiplicity of the operations performedin the exchange.

2. Description of the Prior Art Prior art systems generally included atiming circuit designed for each specific application. These circuitsmade use of the operate and release times of relays or resistancecapacitance circuits in combination with the relays in earlier circuitapplications and later to various types of individual timing circuits ofthe solid state type in conjunction with the relays as for example thatdisclosed in US. Pat. No. 3,732,467.Timing arrangements for a pluralityof functions generally include separate subcircuits operated from acentral time pulse source. Apparatus according to this concept isdisclosed in US. Pat. No. 3,692,962.

SUMMARY OF THE INVENTION This disclosure describes a circuit named theHardware Timer-Scanner which is part of the common logic of theMaintenance Routining Logic (MRL) of No. l EAX Electronic AutomaticExchange. The MRL is the electronic controlling logic of the AutomaticTest referred to as the System (ATS), a software controlled hardwaresubsystem used to routine space-divided equipment (such as lines,trunks, junctors, senders and receivers). The ATS has also beendisclosed in the following related U.S. pa-

tent applications: Multiple use of ATS Test Equipment,

used by itself to perform simple timing of intervals from ms to 2seconds as required by the various routines. The timer is used with thescanner to perform more complicated timing functions, such as outpulsingMF, TCMF, and dial pulse digits in register junctor and MF or TCMFreceiver tests; and for scanning incoming pulse trains; dial pulse fromregister junctors, MF digits from MF senders and supervisory signalsfrom outgoing trunks.

-An important feature of the hardware timer is that basically onecircuit is used to provide the separate functions of simple timing,outpulsing and scanning. It was desirable to combine these functions asmuch as possible, since only one function is required at one time duringthe running of the various routines. This is so because the routinesgenerally test only one function of a space-divided unit at a time,e.g., the local registerjunctor routine requires the functions ofout-pulsing TCMF and dial pulse, and incoming scanning dial pulse, butall at different times.

However some timing for the routines is done by software rather thanhardware, either because the timing interval is long over 2 seconds, orbecause the software is waiting for an interrupt. In the first case,software timing was selected to minimize the size of the hardware timerfor long timing intervals which are seldom used fewer hardware timerflip-flops are required. But for the shorter timing intervals less than2 seconds hardware timing is a must since software scheduling delaysencountered when using the software timer cannot be tolerated. For thelonger timing this fluctuation can be tolerated. The second use ofsoftware timing, i.e.,

BRIEF DESCRIPTION OF THE DRAWING This invention will become moreapparent and be better understood by reference to the followingdescription of an embodiment of the invention taken in conjunction withthe accompanying drawings in which:

FIG. 1 is a block diagram of the functional circuit units of the timer;

FIG. 2 is a chart showing the time pulse tionship;

interrela- FIG. 3 is a simplified schematic of the timer preset circuit;

FIG. 4 is a simplified schematic of the timer control circuit;

FIG. 5 is a simplified schematic of the timer scanner control circuit;

FIG. 6 is a simplified schematic of the scanner control circuit;

FIG. 7 is a simplified schematic of the scanner latch and presetcircuit;

FIG. 8 is a simplified schematic of the last digit latch and controlcircuit;

FIG. 9 is a simplified schematic of the multiplex and MF/TCMF enablecircuit;

FIG. 10 is a simplified schematic of the MF receiver logic anddistributor circuit; and

FIG. 11 illustrates the basic .1 K flip-flop showing the location ofinputs and outputs.

DESCRIPTION OF THE PREFERRED EMBODIMENT General Description A generaldescription of the circuit will be presented next, prior to a detaileddescription of the circuit operation. Referring to FIG. 1, the circuithas been divided into a number of functional blocks. The basic timer/-scanner circuit actually consists of only blocks 11-17. Blocks 18-111have been included to illustrate the two typical uses of thetimer/scanner outpulsing digits and;

scanning incoming digit trains. However, the applications of thetimer/scanner are in no way limited to these functions, as will bediscussed in a later section.

Often during the following discussion, reference will be made toexternal inputs and outputs. In the application of the timer/scanner inthe MRL, the external inputs come from the routining logic, as presetinputs; from the MF test receiver, (and other sources) as inputs to thescanner control for the incoming scanning; or from the output buffer ofthe CPU, as control signals used for clearing the logic and fordiagnostics. The external outputs of the timer/scanner go to the routinglogic, timeout and timeout advance signals; to an MFfICMF test tonesender, and other test units for outpulsing; and to the input buffer ofthe CPU, for relaying test results and for diagnostics.

Certain conventions have been followed in the logic drawings. Gates arenumbered sequentially, with the first digit the same as the figurenumber. Standard NAND logic has been represented, using symbols for NANDgates, negated-input or gates, and inverters as appropriate. Theflip-flops used, see FIG. 11, has three J inputs ANDed together andthree k inputs also ANDed together. The flip-flops also has two presetinputs, clear and clock inputs, plus Q and Q outputs; it clocks on thefalling edge of a pulse.

Timer Presets The timer preset circuit, Block 11 in FIG. I, is shown inmore detail in FIG. 3. It accepts inputs from two sources the scannerpresets, FIG. 7, and from external inputs REG H I MR IN, e.g., thecombining logic of the MRL. It translates a request on one of the inputlines to the appropriate binary value. Several typical values (10, 35,45, 65 and ms) are shown; the hardware timer/scanner in the MRL providesfor many additional values, up to 2 seconds. Note that the binary valuethat results is not exactly the same as theinput in most cases; e.g., aninput for 100 ms results in a preset of 98.

This is due to an offset introduced by using a 1.024 ms clock discussedin more detail later. Also note that some gates not needed for thisexample (37 and 315, and shown unused) would be required for other inputvalues.

Timer Flip-Flops The timer flip-flops, Block 12 of FIG. 1, are shown inFIG. 4. The four flip-flops shown are part of a six flip-flop backwardscounting ripple-down counter clock input of each flip-flop tied toOoutput of preceding flip-flop. For the circuit shown, the timer isdriven from a 1.024 ms input, and can thus time intervals from 1 ms toapproximately l30ms. However more flip-flops can be added to give anincreased range 12 flip-flops are used in the MRL to allow timing toover 4 seconds. After being preset and enabled, the timer countsbackwards to zero. Only one decode, zero is required.

Timer/Scanner Control The timer/scanner control circuit, block 13 ofFIG. I, is presented in more detail in FIGS. 4, 5 and 6. It performs thefollowing functions: presetting, enabling and clearing of the timerflip-flops; generation of output signals upon timeout; control ofoutpulsing and incoming scanning; and control of the timer/scanner fordiagnostic routines. Further discussion of the control will be deferreduntil the detailed circuit operation.

Clock Circuit The clock circuit is shown as block 14 of FIG. 1. All ofthe clock signals, which are shown in FIG. 2, are counted down from an 8MHz crystal. A ring counter provides the basic four clock cycle, clocksA-D. Additional gating yields the remaining clocks. The circuit itself,which is not shown, also provides the clock signals for the remainder ofthe routiner logic in addition to the timer/scanner. The clock are shownin the remaining figures as circles, e.g., for CLK C TRAIL. Oneadditional clock signal, 256 US CLK, not shown in FIG. 2, feeds gate 44on FIG. 4. This clock falls every 8, 32-p.sec cycles at the end of CLKC, and has a 50% duty cycle.

Scanner Latches and Presets As previously mentioned, the timer/scannercan perform both the functions of outpulsing and scanning of incomingpulse trains. For both these purposes the basic scan cycle is dividedinto two periods, T, and T,,.

For MF and TCMF outpulsing, T, is associated with the tone on period,and T,, is associated with the tone off period. For MF receiving thesame holds true. For dial pulse, T, is associated with the break period,T,, with the make period. The provision of two periods allows sendingand receiving of asymmetrical signals; for example in the case of MFoutpulsing the tone on period T, equals 65 ms, and the tone off periodT,, equals 35 ms. Inputs to the scanner from the routiner appear asmomentary grounds on one of the SET XX YY/ZZ leads (FIG. 7 which set oneof the scanner latches shown as block 15 of FIG. 1. The YY/ZZ refer toT, and T,, respectively. At the beginning of the T, or T,, periods, theappropriate preset leads are enabled to preset the timer via the timerpresets, FIG. 3.

Only a few representative latches have been shown in FIG. 7. They are MF100/35, for sending an MF KP digit; MF 65/35, for sending normal MFdigits; TC 45/45, for sending normal TCMF digits; and MFS 100/100, forscanning incoming MF digits. In the latter case, T, and T,, have beenselected to be greater than the signal expected, normally 70/70 in thiscase.

Last Digit Latches and Control The last digit circuit, block 16 of FIG.1, is shown in FIG. 8. At the same time one of the scanner latches isset, one of the last digit latches LDl thrugh LD 16 is set, via the sameinput lead. For outpulsing, the LD latch corresponding to the last digitto be outpulsed is set. For example, to send all 16 possible TCMFdigits, LD 16 is set via SET TC 45/45 (gate For sending digits withdifferent timing, such as MF, external control is required provided bythe sequence state counter in the MRL. To send MF, just MF /35 and LD 1are set to outpulse a KP digit. Following this operation, MF 65/35 andLD 15 are set to outpulse an additional l4 digits, the scanner startsfrom where it left off, at 1.

For incoming scanning, the last digit latch corresponding to one digitpast the number expected is set. Thus, to receive an expected 15 MFdigits, LD 16 is set.

While only three last digit latches are shown in FIG. 8, any number canbe provided.

Scan Counter The scan counter, block 17 of FIG. 1, is also shown in FIG.9. It is simply a binary counter, used to control progression of anoutpulsing or incoming scanning function. Though shown for the circuitas a 5 bit counter with 16 point decode, any size counter can be used asappropriate. The binary output of the counter is available as externaloutputs, which in the case of the routiner are fed into the input bufferof the CPU.

The decimal decode of the scan counter is used to select digits from anoutput buffer for outpulsing, distribute received digits into an inputbuffer during incoming scanning, and stop the scanner operation via thelast digit circuit.

Multiplex:

The digit multiplex, block 18 of FIG. 1, is shown in FIG. 9. It is usedto select one of 16 BCD digits from an external register based on thevalue of the scan counter, and present the selected digit as externaloutputs; which, in the MRL, are fed to a MF/TCMF test tone sender. Allthe digits required need be loaded into the register, e.g., from the CPUonly once, even when different timing is required, e.g., KP digit vsnormal MF since the scan counter is not reset after each scanneroperation.

MF/TCMF Send Enable The MF/TCMF enable circuit, block 19 of FIG. 1 isshown at the bottom of FIG. 9. Depending on whether the scanner isoutpulsing MF or TCMF, determined by the scanner latches, FIG. 7, eitherMF ENAB or TCMF ENAB will go high during T, (tone on period) to enablethe MF/TCMF sender via the external outputs.

MF Receive Logic The MF receive logic, block of FIG. 1 is shown in FIG.10 (lower left). In the case of the MRL, it receives MF digits in BCDform from an MF receiver, external inputs. It provides the true andcomplemented digit values to an external register, e.g., input buffer ofthe CPU. It also provides a signal MF DGT REC which is true when any MFdigit is present.

Distributor The digit distributor, block 1 10 of FIG. 1 is shown in FIG.10. Based on the value of the scan counter, it clocks the appropriatefour flip-flops (one digit) of an external register at the beginning ofeach T, period during incoming MF scanning. Since the incoming MF digitis multipled to all UK inputs of the associated flipflops, this storesthe digit in the appropriate set of fliptlops.

Detailed Description A detailed description of the circuit will bepresented by following through it for several different functions.

Simple Timing The circuit as shown can be used to time intervals from msto 100 ms. A request for a timing interval of 10 ms will appear as amomentary ground on one of 10 the inputs (REG HTMR IN) to gate 31, FIG.3. External gating is such that this pulse is coincident with CLK XTRAIL, X A, B, C or D: CLK C TRAIL was used in most cases in the MRL.This input will cause latch HTMR RUN, gates 54, 55 to set via gates 321and 322. HTMR RUN gates the 256 US CLK to flip-flops 42 and 43 via gate44.

2 usec later, CLK 4 gates the input to set flip-flops FF [2] and FF[8]via gates 39, 310, 313 and 314. FF[2] is shown as gate 413; FF[8] is notshown but would be immediately below FF [4] i n FIG. 4. During the timeI-ITMR SET is low, the J and K inputs of the timer flipflops aredisabled via gates 46 and 47 t o prevent clocking of the flip-flops asthey are preset, Q outputs falling from 1 to 0.

Another 2 usec later, at the end of CLK X TRAIL, the input returns to 1,PTTWSET also returns to 1, and gate 46 is enabled making I-ITMR INPUTENAB high, enabling the J and K inputs of the timer.

Due to the clocking arrangement, negative input, of

t=t,+ 1.024(n-1) ms where t, is the initial clock period, ranging from0.644 ms to 0.868 ms, average 0.756 ms; n is the preset value; and t isthe timed interval from the beginning of the preset to the timeout ofthe timer. For a preset of 10, this works out to be:

min t== 9.860 ms avg t 9972 ms max t =l0.084 ms For larger presets, thebinary preset value is adjusted to compensate for the offset; e.g., fora 100 ms request a preset of 98 is used, resulting in:

min t= 99.972 ms avg t 100.084 ms max t 100.196 ms After being presetand enabled, the timer counts backwards to zero, causing HTMR DEC 0 togo high, it had gone low when the flip-flops were preset, via gates 416and 417. Lead TIMEOUT also goes high, via gates 52 and 53.

4 sec after HTMR DEC 0 becomes true, CLK D TRAIL gates this signal andHTMR RUN, via gate 56, to set the RST HTMR latch, gates 57-58. Another 4#sec later, CLK A enables gate 59 to cause TIMEOUT ADVANCE to go high,for the duration of CLK A. Thus two signals are produced upon a timeout:TIME- OUT, which is a level; and TIMEOUT ADVANCE, which is a pulse,produced during CLK A to be synchronous with the routiners advancecycle. The first signal, TIMEOUT, is often used as a mask in theroutiner to inhibit a false output of a detector for a given period oftime, then enable it following the timeout. The second signal, TIMEOUTADVANCE, used as a strobe, to gate the expected status of an externalsignal, advancing sequence states if true.

12 psec after TIMEOUT ADVANCE returns to 0, CLK C TRAIL enables gate 511resulting in a momentary ground on ITTMRCCR via gates 49 and 410,resetting HTMR RUN via gate 55. Another 4 usec later, m resets RST HTMRvia gates 513, SM and 68, and the circuit returns to normal.

Note that HTMR SET is gated into the reset side of RST HTMR. This is incase a request on one of the external inputs appears during CLK B or CTRAIL immediately following TIMEOUT ADVANCE in CLK A. RST HTMR will bereset, inhibiting generation of the l I signal and clearing of thetimer.

Outpulsing The example used for Outpulsing will be the sending of normalMF digits. It will be assumed that one digit,

i.e., KP, has already been sent, so that the scan counter presently isat 1. Also digits have been loaded into the first 15 digit fields of theoutput buffer, input to the multiplex.

During CLK C TRAIL, a ground is placed on the lead SEI MP 65735, settinglatch MF /35, gates 73 and 74, and latch LD 15, gates 83 and 84. LatchMF 65/35 set causes MF SET to go high, gate 79 and also SCAN ENABLE, viagates 710 and 711. 4 psec after the end of CLK C TRAIL, CLK D TRAILcomes true, causing SCAN GO to be set, via gate 512. 2 usec later, SCANCTR CLK is enabled via gates 69 and 610, the SCAN I flip-flops will bereset. At the end of CLK D TRAIL, SCAN CTR CLK falls, incrementing thescan counter to 2, FIG. 9. 8 psec later, CLK A falls, toggling the SCANI flip-flop, gate 68, so it is set. This causes SCAN ENAB I to go high,which is true during T,. Digit 2, selected from the external buffer viathe multiplex, scan counter 2, is present at the MPLX DGT outputs, fedto the MF sender. MF ENAB also is high, due to ME SET being true alongwith SCAN ENAB I, gates 93, 94. Therefore a digit will be sent out forthe duration of SCAN ENAB I, T, 65 ms.

12 psec after CLK A falls, CLK C TRAIL comes true, causing SCAN GATE Ito go high momentarily, via gates 61 64. This puts a momentary ground onthe 65 MS REQ lead via gate 718. Through the timer preset circuit, FIG.3 this presets the timer exactly as if a request had come in on the REGHTMR IN inputs, (See Section Simple Timing"). HTMR DEC 0 goes low at themiddle of CLK C TRAIL.

At the beginning of CLK D, CLK D LEAD, SCAN G0 is reset via gates 513and 514. However SCAN EN- ABLE still remains true since the scannerIatch MF 65/35 is still set. Meanwhile the timer counts backwards, andHTMR DEC 0 becomes true at the end of a CLK C some 65 ms later. SCAN G0is set again via gate 512 during CLK D TRAIL, RST I-ITMR is not set dueto SCAN ENABLE being low; also TIME OUT is inhibited for the samereason. At the end of CLK D TRAIL, the scan counter is not incremented,since the SCAN I flip-flops is set. SCAN I however is toggled at the endof CLK A, causing SCAN ENAB I to go low. This in turn causes MF ENAB togo low; T tone off period. Thus SCAN I can be thought of as the leastsignificant bit of the scan counter, however more importantly itindicates which part of the scan cycle T, or T,, is in effect.

Also note that during CLK A, flipflops 42 is preset to l by gate 41.This guarantees the next timeout will occur at some integral number of1.024 ms clocks 256 1sec, or as expressed in Section Simple Timing:

t=0.768 +1.024 (n-l) ms This is again done to compensate for the offsetintroduced by the 1.024 ms clock.

At the beginning of CLK C TRAIL, SCAN GATE II is enabled momentarily,causing the timer to be preset via lead 35 MS REQ (gates 66, 67, 719,716 and 717). SCAN G is reset again at the beginning of CLK D. The nexttime the timer goes to zero, after 35 ms, the scan counter will beincremented again since SCAN I is reset. Then digit 3 will be selectedand sent out for 65 ms tone on, 35 ms tone off. This process continuesuntil the last digit The T, period of the last digit is no differentfrom any other, except that after incrementing the scan counter theoutput of gate 810 will go high due to a match between the scan counterand LD 15. Nothing else unusual happens until T,,. Assuming the T,period of digit 15 just timed out, SCAN GO will be set as usual at thebeginning of CLK D TRAIL, and SCAN I will toggle back to zero at the endof CLK A. At the beginning of CLK C TRAIL, SCAN GATE II will be enabledagain. However this time the STOP SCAN latch (gates 812-813) will be setvia gate 811. Meanwhile the timer will be preset for T,, the same as theprevious digits via 35 MS RED.

At the beginning of CLK D, SCAN GO will be reset as before. However, thelead will also go low via gates 814-816 resetting all scanner latchesand last digit latches. The STOP SCAN latch itself will be reset 4 aseclater, CLK D TRAIL.

The timer flip-flops meanwhile will count backwards to zero. This timerhowever when HTMR DEC 0 becomes true, SCAN ENABLE will no longer behigh, since it went low when the scanner latches were reset.

Therefore the same functions that take place at the end' of a simpletiming interval Section Simple Timing will occur, i.e., setting of RSTHTMR latch, generation of TIMEOUT and TIMEOUT ADVANCE signals, andresetting of HTMR RUN and RST HTMR latches. The TIMEOUT ADVANCE signal,which is generated only at the final timeout of an outpulsing operation,is the external signal back to the routiner that the operation iscomplete.

Incoming Scanning Incoming scanning is in many respects similar to theoutpulsing, in terms of the scanners operation. The scan cycle is againdivided into two periods: T, and T,,. However they are selected to belonger than the expected received signal; as long as the incoming signalchanges state before the interval times out, the scanner continues;however if the signal does not change and a timeout occurs, the scannerstops. Also, the last digit latch corresponding to one count greaterthan the number of digits expected is set, so the scanner will also stopif more digits are received than expected.

Scanning of an incoming MF digit train will be used as an example. Atthe start it will be assumed that the scan counter is at zero and SCAN Iis reset. Also, an

MF digit has just been detected, in the routiner, detection of theleading edge of the first MF digit advances sequence states and thescanner is preset in the new sequence state. Therefore during CLK CTRAIL, a ground is placed on the m lead, setting latch MFS 100/100 gates77 and 78 also setting LD 16, gates and 86. T, T,, was selected as to begreater than the nominal 70 ms tone on, 70 ms tone off MF digitsexpected from a regular MF sender. LD 16 was selected as to be onegreater than the number of digits expected (15).

Latch MFS 100/100 set causes MF SCAN SET to go high, also INC SCAN SETvia gate 713, and SCAN EN- ABLE via gate 711. Note that MF DGT REC gate108 will also be high since it was assumed an MP digit had beenreceived.

At the beginning of CLK D TRAIL, two things happened. SCAN GO, gates 515and 516, is set via gate 512, the same as during outpulsing. Inaddition, the lead DELTA RST goes low, due to a mismatch between theincoming signal, output of gate 612 high, and the DELTA latch, gates616-617, detected by an Exclusive-OR circuit, gates 618-620. The DELIARST signal causes H I MR CLR also to go low, which in this firstinstance has no effect, later however this action is an important partof the incoming scanning process.

At the end of CLK D TRAIL, the scan counter is incremented to 1 viagates 69 and 610. Then at the end of CLK A 8 ,usec later, the SCAN lflip-flop is toggled. SCAN DATA I is again generated, as in outpulsingduring CLK C TRAIL; this time the timer flip-flops are preset via thesignal 100 MS SCAN, gates 723, 721, 722. Note that for T, T,,, acombined signal SCAN GATE I II is actually used derived via gate 65.

In addition to presetting the timer, SCAN GATE I also stores theincoming digit into an external register, e.g., input buffer of CPU.Refer to FIG. 10. Depending on the value of the scan counter, a clockpulse generated via gates 101 and 102 is distributed to one of 15 clocklines, one for each digit. Each clock line drives four flip-flops in theregister, storage for one digit. The true and complemented value of theincoming digit gates 102-107 are fed in BCD format to all of theflipflops; the appropriate group of four is clocked via the selectedclock line.

4 ,usec later, at the beginning of CLK D LEAD, the DELTA latch isupdated to reflect the current state of the incoming signal via gates614-615. DELTA INH (gate 621) returns to 1, allowing the SCAN GO latchto be reset also, via gates 513 and 514. It was inhibited from resettinguntil after the DELTA latch was updated since SCAN G0 is fed into gates614-615, and an interlock was required.

' The timer flip-flops then begin to count backwards to zero. However itwill be assumed that the incoming signal changes state in its nominaltime (70 ms), before the timer times out; in this instance the MF DGTREC line FIG. 10 will go low, corresponding to the tone off period ofthe first digit. MF DGT REC low will cause a mismatch again in the deltacircuit during the next CLK D TRAIL; in this case the generation of thefirm signal is significant, as it will clear both the timer flip-flopsand the HTMR RUN latch. The timer flip-flops being cleared causes HTlvRDEC 0 to go high, which in turn causes SCAN GO to set via gate 512.However, since HTMR RUN is reset, gate 51 is not enabled, HTMR RUN beingreset while HTMR DEC and SCAN G0 are true distinguishes between a deltareset due to a change in state of the incoming signal, and a timeoutresulting from no change in state. The remaining actions during thisSCAN GO period are similar to those discussed before, with SCAN I beingreset, beginning of T,,, generation of SCAN GATE II, presetting of thetimer, updating of the DELTA latch, and resetting of SCAN GO.

As long as the incoming signal changes state each interval before thetimer reaches zero, this process continues, with the digit being storedinto the input buffer during T, (actually SCAN GATE I) based on thevalue of the scan counter.

If in fact it continues until the scan counter reaches 16, meaningeither more digits were received than expected, or noise wasencountered, which created additional delta resets, the scanningoperation will cease due to a match between the last digit latch LD 16and the scan counter exactly the same as in outpulsing.

However, if exactly digits are received as expected, then followingpresetting of the timer for the fifteenth T,, period, no additionalchange of state will occur and the timer will continue counting all theway to zero. l-ITMR DEC 0 will come true, and now since HTMR RUN is alsostill set, gate 51 will be enabled during CLK A, causing SCANNER TIMEOUTto go low. In addition, SCAN G0 was set as usual at the beginning of CLKD TRAIL, and the scan counter was incremented, to 16, at the end of CLKD TRAIL.

SCANNER IIMEOUI being low sets the STOP SCAN latch, gates 812-813; theremainder of the cycle is the same as if a last digit match occurredexcept in this case the timer will be preset to T,. Then T, ms later, aTIMEOUT ADVANCE will be generated, the same as for a last digit reset.

In the routiner, the occurrence of a TIMEOUT AD- VANCE following anincoming scanning operation causes an interrupt to the CPU. The CPU thencomes out and reads its input buffer containing the incoming digits.Also via this buffer the CPU reads the status of the scan counter andSCAN I flip-flop to determine the type of termination. If the scancounter equals 16, and SCAN I is set, this implies the proper number ofdigits were received and a scanner timeout occurred as expected. If thescan counter equals 16 and SCAN I is reset, a sixteenth digit waserroneously received causing a last digit match. If the scan counter isless than 16, fewer than the expected digits were received.

Other Applications The above three examples serve to illustrate thethree basic functions of the timer/scanner. However the circuit hasapplications other than these examples which are used by the routiner.The scanner can be used to outpulse dial pulse by adding the appropriatescanner latch and gating for T, 62 ms and T,, 38 ms, and using SCAN ENABI to open a loop during T, break period. For this application, which isbasically what is used in the register junctor routines, the value ofthe dialed digit is selected via the last digit latches, i.e., tooutpulse a dial pulse digit of 2, LD 2 must be set.

The circuit can also be used to receive incoming dial pulse digits. Forthis T, can be 100 ms and T,,, 65 ms each selected to be greater thanthe break and make periods of the dialed digits. In addition, gatingmust be added to one of the inputs of gate 612 to gate the status of abattery feed relay, which follows the incoming digit, ANDed with the newscanner latch for dial pulse scanning, so that the delta circuit willfollow the change in state of the incoming pulses. As in the case of MPreceiving, the value of the scan counter at the end will be one greaterthan the digit sent, and SCAN I should be set.

More complex patterns can be both outpulsed and received with theaddition of external sequencing in the MRL this is accomplished throughthe sequence state counter. This scheme has already been mentioned inregard to MF outpulsing, in which first a KP digit is sent by settinglatches MF /35 and LD 1, and loading digit 1 with a value of I 1.Following the TIMEOUT ADVANCE signal, the external control advancessequence state and sets latch MF 65/35 and LD 15 to send 14 additionalMF digits with normal timing.

The MRL also uses external sequence control to scan supervisory signals.For this purpose, in addition to the scanner and latch digit latches,still additional gating must be added to the third input of gate 612, inthis case so the delta circuit can follow changes of state of thesupervisory relay. One of the incoming signals scanned coming from anonsynchronous test line consists of: approximately a. 1% secondsoff-hook b. second on-hook c. 1% second off-hook d. 3 flashes of IPMBetween c and d a dynamic change of the scanner latches is done to adaptto the changing pattern.

Other applications are of course possible, but the above examplesillustrate the uses of the circuit. In general, where it has shownspecific sizes for various circuit blocks such as the number of timerflip-flops, size of the scan counter, multiplex, distributor, or numberof scanner or last digit latches it was only for purpose of example andin fact no limit exists in the general architecture on these signs.

Also, the last digit latches could be implemented as a register, whichcould be loaded from the CPU (along with digit values), and equippedwith a matching circuit between the output of this register and theoutput of the scan counter. This would allow the number of digits to besent out to be variable rather than hardwired, without detracting fromthe general architecture of the timer/scanner.

Maintenance Considerations In its application in the routining logic ofNo. l EAX, it is imperative that the timer/scanner be maintainable, aswith any electronic subsystem in NO. I EAX. For this reason a minimalamount of circuitry was added to allow finding faults in thetimer/scanner via simple diagnostic routines.

The fundamental signal for controlling diagnostics of the timer scanneris the I-ITMR ROUT lead, controlled by an external source (e.g., CPU).When it is true gate 46 is disabled, forcing HTMR INPUT ENAB low, whichinhibits running of the timer flip-flops; but it does not prevent theirbeing preset. Thus the timer flipflops can be used as a diagnosticregister.

To check the various preset values of the timer, first HTMR ROUT is madeI, and then one of the external request lines REG HTMR IN is groundedmomentarily (in the MRL, this is done via a test advance mode" of thesequence state counter (as outlined in application Ser. No. 348,806).The flip-flops of the timer are then checked for the appropriate preset,a ground is placed momentarily on the CLEAR lead to reset the flip-flopsand the sequence is repeated for the next input.

To check for the proper setting of the scanner latches, and operation ofthe scanner presets, the same basic sequence can be followed, beginningwith setting of the appropriate scanner latch. This will check the T,preset since SCAN I will toggle before the preset occurs. To check the Tpreset for each latch, the same sequence is repeated with the lead DISSCAN I grounded (gate 68). This disables setting of the SCAN Iflip-flop, thus the T preset will occur instead of T,.

Following checking of all the presets, the operation of the timer itselfis checked via a simple circuit. HTMR ROUT is made high again, alongwith ENAB PS ALL ONES. During the next CLK C TRAIL gate 48 is enabled,causingPS ALL ONES to go low, in turn presetting all of the timerflip-flops and setting the HTMR RUN flip-flops gates 321-322. HTMR ROUTis then made low ENAB PS ALL ONES is still high. This enables the timerflip-flops via gates 45, 46, and 47. At the same time the CPU resetsHTMR ROUT, it collects real time from the systems real time clock. Thetimer counts backwards to zero, the same as any other simple timingoperation. However when the TIMEOUT AD- VANCE signal occurs, it causesan interrupt to the CPU via gate 411. The diagnostic routine collectsreal time again and compares the difference between the two values ofreal time with the running time of the timer for a preset of all ones,129.8 ms for the timer shown; 4.19 seconds for the timer in the MRL.Since any fault in the flip-flops will cause an error of a factor of atleat two, or cause the timer not to function at al, the slight ambiguityintroduced by the software real time clock (16.67ms) is of noconsequence.

Checking the last digit latches can be done in one of two ways. Thefirst is a functional check, in which the scanner is preset normally toperform a particular task and at the end the scan counter is checked ifit matches the last digit latch set. However this requires time. The

second scheme, though quicker, requires gating of the status of all thelast digit latches to the external input buffer of the CPU. Then HTMRROUT can be made 1, freezing the scanner, and after setting the latchestheir state can be examined via the CPU. This second scheme was used inthe MRL.

This leaves only the scan counter and the delta circuit of the basictimer/scanner to be checked. They can be routined together provided theexternal control can simulate one of the signals gated into the deltacircuit. With HTMR ROUT held at 1, and the appropriate scanner latchset, it is only necessary to toggle the in coming signals successivelyto exercise the delta circuit. In addition, the SCAN l flip-flop shouldfollow the incoming signal, and the scan counter should increment eachtime the SCAN l flip-flop sets.

The remaining circuits such as the multiplex, distributor, etc. can bemost easily checked functionally, i.e., verifying that they returnexpected results consistently in actual use.

What is claimed is:

l. A variable time interval measuring circuit for measuring a timeinterval as set by external control apparatus and comprising: a sourceof time pulses, a time interval binary counter means operably connectedto said source of timed pulses, setting means operated by said externalcontrol apparatus to set said counter to a particular count, a decodemeans operated to produce an output upon said counter reaching saidparticular count, said decode means being arranged to decode only an allzero condition of said counter, a first plurality of register means, afirst and a second coding means connecting each said register means tosaid setting means, whereby each said register means upon opera tion bysaid external control apparatus is effective to control said timeinterval measuring circuit to measure a first particular interval and asecond particular interval, a second plurality of register means, eachof said second plurality of register means upon operation by saidexternal control apparatus effective to permit the restart of said firstregister means a plurality of times corresponding to the settingthereof, connect means connecting said second plurality of registermeans to said first plurality of register means, and control meansconnected to said second plurality of register means and operated fromsaid output of said decode means to register an operation thereof.

2. A variable time interval measuring circuit as claimed in claim 1wherein said second plurality of register means comprise a plurality oflatches, and said control means includes a counter means operativelyconnected to said decode means and to said second plurality of registermeans to reset said second register means upon said counter reaching acount corresponding to said register means.

1. A variable time interval measuring circuit for measuring a timeinterval as set by external control apparatus and comprising: a sourceof time pulses, a time interval binary counter means operably connectedto said source of timed pulses, setting means operated by said externalcontrol apparatus to set said counter to a particular count, a decodemeans operated to produce an output upon said counter reaching saidparticular count, said decode means being arranged to decode only an allzero condition of said counter, a first plurality of register means, afirst and a second coding means connecting each said register means tosaid setting means, whereby each said register means upon operation bysaid external control apparatus is effective to control said timeinterval measuring circuit to measure a first particular interval and asecond particular interval, a second plurality of register means, eachof said second plurality of register means upon operation by saidexternal control apparatus effective to permit the restart of said firstregister means a plurality of times corresponding to the settingthereof, connect means connecting said second plurality of registermeans to said first plurality of register means, and control meansconnected to said second plurality of register means and operated fromsaid output of said decode means to register an operation thereof.
 2. Avariable time interval measuring circuit as claimed in claim 1 whereinsaid second plurality of register means comprise a plurality of latches,and said control means includes a counter means operatively connected tosaid decode means and to said second plurality of register means toreset said second register means upon said counter reaching a countcorresponding to said register means.